diff options
| author | bhgv <bhgv.empire@gmail.com> | 2020-05-10 02:59:23 +0300 |
|---|---|---|
| committer | bhgv <bhgv.empire@gmail.com> | 2020-05-10 02:59:23 +0300 |
| commit | 31b4edc67b75658ce5e2d41f2fc87331f4b26d49 (patch) | |
| tree | a7b6ea659fe62e0a7239f29170024f524595fb4d /lib9/setfcr-FreeRTOS-riscv64.c | |
| parent | c76314f0f38f4ed028610a6db4452879a556b35f (diff) | |
a try to add support of FreeRTOS riscV-64 (k210 cpu). first step
Diffstat (limited to 'lib9/setfcr-FreeRTOS-riscv64.c')
| -rw-r--r-- | lib9/setfcr-FreeRTOS-riscv64.c | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/lib9/setfcr-FreeRTOS-riscv64.c b/lib9/setfcr-FreeRTOS-riscv64.c new file mode 100644 index 0000000..0ed32c6 --- /dev/null +++ b/lib9/setfcr-FreeRTOS-riscv64.c @@ -0,0 +1,64 @@ +/* + * Linux 386 fpu support + * Mimic Plan9 floating point support + */ + +#include "lib9.h" + +void +setfcr(ulong fcr) +{ +#if 0 + __asm__( "xorb $0x3f, %%al\n\t" + "pushw %%ax\n\t" + "fwait\n\t" + "fldcw (%%esp)\n\t" + "popw %%ax\n\t" + : /* no output */ + : "al" (fcr) + ); +#endif +} + +ulong +getfcr(void) +{ + ulong fcr = 0; + +#if 0 + __asm__( "pushl %%eax\n\t" + "fwait\n\t" + "fstcw (%%esp)\n\t" + "popl %%eax\n\t" + "xorb $0x3f, %%al\n\t" + : "=a" (fcr) + : "eax" (fcr) + ); +#endif + return fcr; +} + +ulong +getfsr(void) +{ + ulong fsr = -1; + +#if 0 + __asm__( "fwait\n\t" + "fstsw (%%eax)\n\t" + "movl (%%eax), %%eax\n\t" + "andl $0xffff, %%eax\n\t" + : "=a" (fsr) + : "eax" (&fsr) + ); +#endif + return fsr; +} + +void +setfsr(ulong fsr) +{ +#if 0 + __asm__("fclex\n\t"); +#endif +} |
