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authorMDC Service <michael.schmid@mdc-service.de>2022-05-23 11:17:34 +0200
committerGitHub <noreply@github.com>2022-05-23 11:17:34 +0200
commit74a0003fea4087de8e9f03b6f828c45d255bcd4a (patch)
tree1b4615232dcac918fcc47cbd3c6ed54014fb38b7 /software/michi_funcs/board_rev_A.cpp
parentd2f3c7c9e17895ae43caed761f941a30e4e5eed6 (diff)
initial check in firmware files
Diffstat (limited to 'software/michi_funcs/board_rev_A.cpp')
-rw-r--r--software/michi_funcs/board_rev_A.cpp38
1 files changed, 38 insertions, 0 deletions
diff --git a/software/michi_funcs/board_rev_A.cpp b/software/michi_funcs/board_rev_A.cpp
new file mode 100644
index 0000000..f71e27a
--- /dev/null
+++ b/software/michi_funcs/board_rev_A.cpp
@@ -0,0 +1,38 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "driver/gpio.h"
+#include "schrank_ant_pcb.h" //contains setting of board revision
+
+#ifndef ESP32_BOARD_REV_B
+
+void io_init(void)
+{
+
+#define GPO_BIT_MASK (1ULL << PHY_PWR)
+ gpio_config_t o_conf;
+ o_conf.intr_type = GPIO_INTR_DISABLE;
+ o_conf.mode = GPIO_MODE_OUTPUT;
+ o_conf.pin_bit_mask = GPO_BIT_MASK;
+ o_conf.pull_down_en = GPIO_PULLDOWN_ENABLE;
+ o_conf.pull_up_en = GPIO_PULLUP_DISABLE;
+ gpio_config(&o_conf);
+ gpio_set_level((gpio_num_t) PHY_PWR, 1);
+
+ // inputs
+ /*
+ #define GPI_BIT_MASK ((1ULL << SWITCH)|(1ULL << SWITCH))
+ gpio_config_t i_conf;
+ i_conf.intr_type = GPIO_INTR_DISABLE;
+ i_conf.mode = GPIO_MODE_INPUT;
+ i_conf.pin_bit_mask = GPI_BIT_MASK;
+ i_conf.pull_down_en = GPIO_PULLDOWN_DISABLE;
+ i_conf.pull_up_en = GPIO_PULLUP_DISABLE;
+ gpio_config(&i_conf);
+ */
+}
+
+#endif