diff options
| author | MDC Service <michael.schmid@mdc-service.de> | 2022-05-23 11:05:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-23 11:05:34 +0200 |
| commit | d2f3c7c9e17895ae43caed761f941a30e4e5eed6 (patch) | |
| tree | 0d40791eab7a7e833355ec6b65fa9d9e2bec4a38 /hardware/ESP32_RaspiFF_LAN8720ETH_V2.pro | |
| parent | f2f0f0dc260e34b441200b34dc5b3a8ad84c19ad (diff) | |
initaial check in EsPiFF V2 files
Diffstat (limited to 'hardware/ESP32_RaspiFF_LAN8720ETH_V2.pro')
| -rw-r--r-- | hardware/ESP32_RaspiFF_LAN8720ETH_V2.pro | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/hardware/ESP32_RaspiFF_LAN8720ETH_V2.pro b/hardware/ESP32_RaspiFF_LAN8720ETH_V2.pro new file mode 100644 index 0000000..8e669f3 --- /dev/null +++ b/hardware/ESP32_RaspiFF_LAN8720ETH_V2.pro @@ -0,0 +1,94 @@ +update=17.12.2019 (вт) 9:44:47 EET +version=1 +last_client=kicad +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[eeschema] +version=1 +LibDir= +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName=./ +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_WriteFile=0 +ERC_TestSimilarLabels=1 +ERC_CheckUniqueGlobalLabels=1 +ERC_CheckBusDriverConflicts=1 +ERC_CheckBusEntryConflicts=1 +ERC_CheckBusToBusConflicts=1 +ERC_CheckBusToNetConflicts=1 +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead=ESP32-GATEWAY_Rev_G.net +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.127 +MinViaDiameter=0.7 +MinViaDrill=0.4 +MinMicroViaDiameter=0 +MinMicroViaDrill=0 +MinHoleToHole=0.3048 +TrackWidth1=0.2032 +TrackWidth2=0.254 +TrackWidth3=0.3048 +TrackWidth4=0.508 +TrackWidth5=0.762 +TrackWidth6=1.016 +TrackWidth7=1.27 +TrackWidth8=1.524 +TrackWidth9=1.778 +ViaDiameter1=0.7 +ViaDrill1=0.4 +ViaDiameter2=0.7 +ViaDrill2=0.4 +ViaDiameter3=0.8 +ViaDrill3=0.5 +ViaDiameter4=0.9 +ViaDrill4=0.6 +dPairWidth1=0.2032 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.15 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.254 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.254 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0.2 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=2 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=2 + |