diff options
| author | Drahflow <drahflow@gmx.de> | 2013-09-29 13:19:43 +0200 |
|---|---|---|
| committer | Drahflow <drahflow@gmx.de> | 2013-09-29 13:19:43 +0200 |
| commit | cd680c6d4bb37213e1dbe0df5c87c6f8ea1b04eb (patch) | |
| tree | bca90cab67661191273ae9f446c843b4bc4682b1 /elymas/lib | |
| parent | 6654eba47e84a08864605065fd90bb65730516b4 (diff) | |
13% faster with (some) inline arithmetics
Diffstat (limited to 'elymas/lib')
| -rw-r--r-- | elymas/lib/sys/opt.ey | 158 |
1 files changed, 158 insertions, 0 deletions
diff --git a/elymas/lib/sys/opt.ey b/elymas/lib/sys/opt.ey index a1c835f..8ac7980 100644 --- a/elymas/lib/sys/opt.ey +++ b/elymas/lib/sys/opt.ey @@ -245,6 +245,163 @@ } /rewriteConstantDot deffst { _ ==logic + 3 logic len range { ==i + i logic * ==entry + 0 entry * ==action + i 1 sub logic * ==last + i 2 sub logic * ==secondLast + i 3 sub logic * ==thirdLast + + [ + { action CALL streq + { 1 entry * "*" | +rawCodeAddress eq }' andif + { 0 last * PUSH streq }' andif + { 1 last * |add +rawAddress eq }' andif + { + 0 secondLast * STATICTYPED streq + { 4 secondLast * sys .typed .type 0 eq }' andif + 0 secondLast * PUSH streq + { 1 secondLast * sys .typed .type 0 eq }' andif + or + }' andif + { + 0 thirdLast * STATICTYPED streq + { 4 thirdLast * sys .typed .type 0 eq }' andif + 0 thirdLast * PUSH streq + { 1 thirdLast * sys .typed .type 0 eq }' andif + or + }' andif + }' { + [ NATIVE [ + /rcx :popqReg + 63 /rcx :btrqImm8Reg + [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8 + 8 /rcx /rcx :movqMemDisp8Reg + + /rdx :popqReg + 63 /rdx :btrqImm8Reg + [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8 + 8 /rdx /rdx :movqMemDisp8Reg + + /rcx /rdx :addqRegReg + + /rdx /rax :movqRegReg + 32 /rax :shrqImm8Reg + + [ + 63 /rdx :btsqImm8Reg + /rdx :pushqReg + 0 :jmpRel8 + ] len :jnzRel8 + + 63 /rdx :btsqImm8Reg + /rdx :pushqReg + + [ + /rdx :pushqReg + ::internalAllocateInteger /rax :movqImmReg + /rax :callqReg + 8 /rax :popqMemDisp8 + /rax :pushqReg + ] len :jmpRel8 + + /rdx :pushqReg + ::internalAllocateInteger /rax :movqImmReg + /rax :callqReg + 8 /rax :popqMemDisp8 + /rax :pushqReg + ] ] i logic =[] + [ NOP ] i 1 sub logic =[] + } + + { action CALL streq + { 1 entry * "*" | +rawCodeAddress eq }' andif + { 0 last * PUSH streq }' andif + { 1 last * |le +rawAddress eq }' andif + { + 0 secondLast * STATICTYPED streq + { 4 secondLast * sys .typed .type 0 eq }' andif + 0 secondLast * PUSH streq + { 1 secondLast * sys .typed .type 0 eq }' andif + or + }' andif + { + 0 thirdLast * STATICTYPED streq + { 4 thirdLast * sys .typed .type 0 eq }' andif + 0 thirdLast * PUSH streq + { 1 thirdLast * sys .typed .type 0 eq }' andif + or + }' andif + }' { + [ NATIVE [ + /rcx :popqReg + 63 /rcx :btrqImm8Reg + [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8 + 8 /rcx /rcx :movqMemDisp8Reg + + /rdx :popqReg + 63 /rdx :btrqImm8Reg + [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8 + 8 /rdx /rdx :movqMemDisp8Reg + + /rsi /rsi :xorqRegReg + /rcx /rdx :cmpqRegReg + + [ /rsi :incqReg ] len :jnleRel8 + /rsi :incqReg + + 63 /rsi :btsqImm8Reg + /rsi :pushqReg + ] ] i logic =[] + [ NOP ] i 1 sub logic =[] + } + + { action CALL streq + { 1 entry * "*" | +rawCodeAddress eq }' andif + { 0 last * PUSH streq }' andif + { 1 last * |lt +rawAddress eq }' andif + { + 0 secondLast * STATICTYPED streq + { 4 secondLast * sys .typed .type 0 eq }' andif + 0 secondLast * PUSH streq + { 1 secondLast * sys .typed .type 0 eq }' andif + or + }' andif + { + 0 thirdLast * STATICTYPED streq + { 4 thirdLast * sys .typed .type 0 eq }' andif + 0 thirdLast * PUSH streq + { 1 thirdLast * sys .typed .type 0 eq }' andif + or + }' andif + }' { + [ NATIVE [ + /rcx :popqReg + 63 /rcx :btrqImm8Reg + [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8 + 8 /rcx /rcx :movqMemDisp8Reg + + /rdx :popqReg + 63 /rdx :btrqImm8Reg + [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8 + 8 /rdx /rdx :movqMemDisp8Reg + + /rsi /rsi :xorqRegReg + /rcx /rdx :cmpqRegReg + + [ /rsi :incqReg ] len :jnlRel8 + /rsi :incqReg + + 63 /rsi :btsqImm8Reg + /rsi :pushqReg + ] ] i logic =[] + [ NOP ] i 1 sub logic =[] + } + ] conds + } each + } /rewriteArithmetics deffst + + { _ ==logic 1 logic len range { ==i i logic * ==entry 0 entry * ==action i 1 sub logic * ==last [ { action CALL streq @@ -531,6 +688,7 @@ rewriteConstantEquals } rep rewriteConstantDot + rewriteArithmetics rewriteConstantStar rewriteStackOps { =*entry 0 entry ==action |