diff options
| author | Drahflow <drahflow@gmx.de> | 2015-06-09 14:36:00 +0200 |
|---|---|---|
| committer | Drahflow <drahflow@gmx.de> | 2015-06-09 14:36:00 +0200 |
| commit | af06ddf8329611f4f2e073f308ae3bb23957fdb3 (patch) | |
| tree | 8d3ce1c0e8395b7b44b9f96d828b03d5f1600b12 /compiler | |
| parent | 7e7909ad30ae6b9209a6821d2487f7d1f655dd45 (diff) | |
Some instruction shuffling
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/elymasAsmLib.ey | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/compiler/elymasAsmLib.ey b/compiler/elymasAsmLib.ey index 795e9a1..191f1fb 100644 --- a/compiler/elymasAsmLib.ey +++ b/compiler/elymasAsmLib.ey @@ -361,13 +361,11 @@ # freelist code must not modify rbx, rdi # FIXME, find why lib/sys/opt.ey requires unmodified rdi # @takeFromFreelist - /rdi /rax :movqRegReg - /rax :decqReg + 1 neg /rdi /rax :leaqMemDisp8Reg /rax /rax :bsrqRegReg # compute log_2(rdi) - /rax :incqReg freeLists /rsi :movqImmReg - 8 /rax /rsi /rcx :leaqMemIndexScaleReg # load correct freelist start + 8 8 /rax /rsi /rcx :leaqMemIndexScaleDisp8Reg # load correct freelist start /rax /rax :xorqRegReg /rcx /rax :orqMemReg # load entry /freeListUseful :jnzLbl8 @@ -394,8 +392,7 @@ %F0 /rsi :andqImm8Reg # reset lower 4 bit /returnFreeListBlock :jzLbl8 - /rax /rdi /rdx :leaqMemIndexReg - 8 /rdx :addqImm8Reg + 8 1 /rax /rdi /rdx :leaqMemIndexScaleDisp8Reg %F0 /rdx :andqImm8Reg # align on 16 byte cell # rdx == start of remaining block |