diff options
| author | Drahflow <drahflow@gmx.de> | 2015-06-11 16:37:50 +0200 |
|---|---|---|
| committer | Drahflow <drahflow@gmx.de> | 2015-06-11 16:37:50 +0200 |
| commit | 5bbcdb3faeb11a93483bf2fbba46721c74a115bb (patch) | |
| tree | 532571c10efb6be7d3adb3ea4340ef38b947663f /compiler | |
| parent | 291a901b8323bf6b00e8eb8b3faec88f97ad3130 (diff) | |
Fixed(?) memory bug
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/elymasAsmLib.ey | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/compiler/elymasAsmLib.ey b/compiler/elymasAsmLib.ey index c3ce9d2..ae47a9e 100644 --- a/compiler/elymasAsmLib.ey +++ b/compiler/elymasAsmLib.ey @@ -392,7 +392,7 @@ %F0 /rsi :andqImm8Reg # reset lower 4 bit /returnFreeListBlock :jzLbl8 - 8 1 /rax /rdi /rdx :leaqMemIndexScaleDisp8Reg + 15 1 /rax /rdi /rdx :leaqMemIndexScaleDisp8Reg %F0 /rdx :andqImm8Reg # align on 16 byte cell # rdx == start of remaining block @@ -436,7 +436,7 @@ /rcx /rsi :btrqRegMem # reset mark bit 4 /rcx :shlqImm8Reg - 8 1 /rdi /rcx /rcx :leaqMemIndexScaleDisp8Reg + 15 1 /rdi /rcx /rcx :leaqMemIndexScaleDisp8Reg # align on 16 byte cell 4 /rcx :shrqImm8Reg # rcx == cell number of first cell of next block /rcx /rbp :cmpqRegReg @@ -545,7 +545,7 @@ @freeBlockStartFound %C0 /rbx :andqImm8Reg /rax /rbx :addqRegReg - 8 /rdi /rsi :leaqMemDisp8Reg + 15 /rdi /rsi :leaqMemDisp8Reg # round up align to cells 4 /rsi :shrqImm8Reg # rsi == number of cells needed overall 1 neg 1 /rbx /rsi /rsi :leaqMemIndexScaleDisp8Reg # rsi == last cell we need to allocate /rsi /rbp :cmpqRegReg |