aboutsummaryrefslogtreecommitdiff
path: root/compiler/elymasAsm.ey
diff options
context:
space:
mode:
authorDrahflow <drahflow@gmx.de>2013-01-22 18:52:17 +0100
committerDrahflow <drahflow@gmx.de>2013-01-22 18:52:17 +0100
commite5b6407246b3fd64014f92e80679274cb1a7bfde (patch)
treeb8cfb349372cf0a651b2669c087b4cfbc1161b9e /compiler/elymasAsm.ey
parent38c6689e33361193d3791a6fc6052824208c9cf7 (diff)
More standard functions
grep.ey now compiling
Diffstat (limited to 'compiler/elymasAsm.ey')
-rw-r--r--compiler/elymasAsm.ey99
1 files changed, 99 insertions, 0 deletions
diff --git a/compiler/elymasAsm.ey b/compiler/elymasAsm.ey
index 78d716b..f09a47f 100644
--- a/compiler/elymasAsm.ey
+++ b/compiler/elymasAsm.ey
@@ -275,10 +275,90 @@
1 dst /none src rex
%0F
+ %46
+ dst src modrm11
+ } /cmovnaqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
%43
dst src modrm11
} /cmovaeqRegReg deff
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %42
+ dst src modrm11
+ } /cmovaeqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %4F
+ dst src modrm11
+ } /cmovgqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %4E
+ dst src modrm11
+ } /cmovngqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %4D
+ dst src modrm11
+ } /cmovgeqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %4C
+ dst src modrm11
+ } /cmovngeqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %45
+ dst src modrm11
+ } /cmovnzqRegReg deff
+
+ { ==dst ==src
+ src bit64assert
+ dst bit64assert
+
+ 1 dst /none src rex
+ %0F
+ %44
+ dst src modrm11
+ } /cmovzqRegReg deff
+
{
%A6
} /cmpsb deff
@@ -635,6 +715,17 @@
1 idx mem sib
} /movqRegMemIndex deff
+ { ==mem ==idx ==scale ==reg
+ reg bit64assert
+ mem bit64assert
+ idx bit64assert
+
+ 1 reg idx mem rex
+ %89
+ reg /sib modrm00
+ scale idx mem sib
+ } /movqRegMemIndexScale deff
+
{ ==dst ==src
src bit64assert
dst bit64assert
@@ -671,6 +762,14 @@
/four reg modrm11
} /mulqReg deff
+ { ==reg
+ reg bit64assert
+
+ 1 /none /none reg rex
+ %F7
+ /three reg modrm11
+ } /negqReg deff
+
{ ==mem ==i
mem bit64assert
i 256 lt assert