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authorDrahflow <drahflow@gmx.de>2013-08-12 23:49:27 +0200
committerDrahflow <drahflow@gmx.de>2013-08-12 23:49:27 +0200
commit6f056dfa3531a9ddea4bc4369f5f19e07ffc85e2 (patch)
treed78baa2edf87070c47ad42961ae0d373c1f5c055 /compiler/elymasAsm.ey
parent0133daad6426cc8b50000d79c27de8ebffe34fc9 (diff)
Some optimizations to the allocator
Diffstat (limited to 'compiler/elymasAsm.ey')
-rw-r--r--compiler/elymasAsm.ey51
1 files changed, 51 insertions, 0 deletions
diff --git a/compiler/elymasAsm.ey b/compiler/elymasAsm.ey
index 2d9f7b8..0148faa 100644
--- a/compiler/elymasAsm.ey
+++ b/compiler/elymasAsm.ey
@@ -392,6 +392,54 @@
reg mem modrm00
} /addlMemReg deff
+ { ==opcode2 ==opcode1 ==mnemonic
+ { ==reg2 ==reg1
+ reg2 bit64assert
+ reg1 bit64assert
+
+ 1 reg1 /none reg2 rex
+ opcode1
+ opcode2
+ reg1 reg2 modrm11
+ } mnemonic /qRegReg defOp
+
+ memoryAddressingVariants keys { ==variant memoryAddressingVariants variant . =*parse
+ { parse ==mem ==reg
+ reg bit64assert
+
+ 1 reg mem .idx mem .base rex
+ opcode1
+ opcode2
+ reg mem .encode
+ } mnemonic /qReg variant cat defOp
+ } each
+ } /defAsmBtq deff
+
+ { ==modrmOpcode ==opcode2 ==opcode1 ==mnemonic
+ { ==reg ==i
+ reg bit64assert
+
+ 1 /none /none reg rex
+ opcode1
+ opcode2
+ modrmOpcode reg modrm11
+ i imm8
+ } mnemonic /qImm8Reg defOp
+
+ memoryAddressingVariants keys { ==variant memoryAddressingVariants variant . =*parse
+ { parse ==mem ==imm
+ 1 /none mem .idx mem .base rex
+ opcode1
+ opcode2
+ modrmOpcode mem .encode
+ imm imm8
+ } mnemonic /qImm8 variant cat defOp
+ } each
+ } /defAsmBtqImm deff
+
+ /adc %11 defAsmAddq
+ /adc /two defAsmAddImm
+
/add %01 defAsmAddq
/add /zero defAsmAddImm
@@ -399,6 +447,9 @@
/and %21 defAsmAddq
/and /four defAsmAddImm
+ /bt %0F %A3 defAsmBtq
+ /bt %0F %BA /four defAsmBtqImm
+
{ ==off
%E8
off imm32