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authorDrahflow <drahflow@gmx.de>2013-09-29 20:30:25 +0200
committerDrahflow <drahflow@gmx.de>2013-09-29 20:30:25 +0200
commit67fb3a739ca5a95af7e17abd20edb38a823c4cdc (patch)
treeec7b70300327c073ac8804e4978588cb46c5a425
parent0e4db45b56b6f384b251dd64ede92f928fd16422 (diff)
Code cleanup
-rw-r--r--elymas/lib/sys/opt.ey214
1 files changed, 79 insertions, 135 deletions
diff --git a/elymas/lib/sys/opt.ey b/elymas/lib/sys/opt.ey
index bd1f9ae..3de3056 100644
--- a/elymas/lib/sys/opt.ey
+++ b/elymas/lib/sys/opt.ey
@@ -257,152 +257,96 @@
i 2 sub logic * ==secondLast
i 3 sub logic * ==thirdLast
- [
- { action CALL streq
- { 1 entry * "*" | +rawCodeAddress eq }' andif
- { 0 last * PUSH streq }' andif
- { 1 last * |add +rawAddress eq }' andif
- {
- 0 secondLast * STATICTYPED streq
- { 4 secondLast * sys .typed .type 0 eq }' andif
- 0 secondLast * PUSH streq
- { 1 secondLast * sys .typed .type 0 eq }' andif
- or
- }' andif
- {
- 0 thirdLast * STATICTYPED streq
- { 4 thirdLast * sys .typed .type 0 eq }' andif
- 0 thirdLast * PUSH streq
- { 1 thirdLast * sys .typed .type 0 eq }' andif
- or
- }' andif
- }' {
- [ NATIVE [
- /rcx :popqReg
- 63 /rcx :btrqImm8Reg
- [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
- 8 /rcx /rcx :movqMemDisp8Reg
-
- /rdx :popqReg
- 63 /rdx :btrqImm8Reg
- [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
- 8 /rdx /rdx :movqMemDisp8Reg
-
- /rcx /rdx :addqRegReg
+ { ==e
+ 0 e * STATICTYPED streq { 4 e * sys .typed .type 0 eq }' andif
+ 0 e * PUSH streq { 1 e * sys .typed .type 0 eq }' andif
+ or
+ } /holdsInt deffd
+
+ action CALL streq
+ { 1 entry * "*" | +rawCodeAddress eq }' andif
+ { 0 last * PUSH streq }' andif
+ { secondLast holdsInt }' andif
+ { thirdLast holdsInt }' andif
+ {
+ [
+ { 1 last * |add +rawAddress eq }' {
+ [ NATIVE [
+ /rcx :popqReg
+ 63 /rcx :btrqImm8Reg
+ [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
+ 8 /rcx /rcx :movqMemDisp8Reg
+
+ /rdx :popqReg
+ 63 /rdx :btrqImm8Reg
+ [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
+ 8 /rdx /rdx :movqMemDisp8Reg
+
+ /rcx /rdx :addqRegReg
+
+ /rdx /rax :movqRegReg
+ 32 /rax :shrqImm8Reg
+
+ [
+ 63 /rdx :btsqImm8Reg
+ /rdx :pushqReg
+ 0 :jmpRel8
+ ] len :jnzRel8
- /rdx /rax :movqRegReg
- 32 /rax :shrqImm8Reg
-
- [
63 /rdx :btsqImm8Reg
/rdx :pushqReg
- 0 :jmpRel8
- ] len :jnzRel8
- 63 /rdx :btsqImm8Reg
- /rdx :pushqReg
+ [
+ /rdx :pushqReg
+ ::internalAllocateInteger /rax :movqImmReg
+ /rax :callqReg
+ 8 /rax :popqMemDisp8
+ /rax :pushqReg
+ ] len :jmpRel8
- [
/rdx :pushqReg
::internalAllocateInteger /rax :movqImmReg
/rax :callqReg
8 /rax :popqMemDisp8
/rax :pushqReg
- ] len :jmpRel8
-
- /rdx :pushqReg
- ::internalAllocateInteger /rax :movqImmReg
- /rax :callqReg
- 8 /rax :popqMemDisp8
- /rax :pushqReg
- ] ] i logic =[]
- [ NOP ] i 1 sub logic =[]
- }
-
- { action CALL streq
- { 1 entry * "*" | +rawCodeAddress eq }' andif
- { 0 last * PUSH streq }' andif
- { 1 last * |le +rawAddress eq }' andif
- {
- 0 secondLast * STATICTYPED streq
- { 4 secondLast * sys .typed .type 0 eq }' andif
- 0 secondLast * PUSH streq
- { 1 secondLast * sys .typed .type 0 eq }' andif
- or
- }' andif
- {
- 0 thirdLast * STATICTYPED streq
- { 4 thirdLast * sys .typed .type 0 eq }' andif
- 0 thirdLast * PUSH streq
- { 1 thirdLast * sys .typed .type 0 eq }' andif
- or
- }' andif
- }' {
- [ NATIVE [
- /rcx :popqReg
- 63 /rcx :btrqImm8Reg
- [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
- 8 /rcx /rcx :movqMemDisp8Reg
-
- /rdx :popqReg
- 63 /rdx :btrqImm8Reg
- [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
- 8 /rdx /rdx :movqMemDisp8Reg
-
- /rsi /rsi :xorqRegReg
- /rcx /rdx :cmpqRegReg
-
- [ /rsi :incqReg ] len :jnleRel8
- /rsi :incqReg
-
- 63 /rsi :btsqImm8Reg
- /rsi :pushqReg
- ] ] i logic =[]
- [ NOP ] i 1 sub logic =[]
- }
+ ] ] i logic =[]
+ [ NOP ] i 1 sub logic =[]
+ }
- { action CALL streq
- { 1 entry * "*" | +rawCodeAddress eq }' andif
- { 0 last * PUSH streq }' andif
- { 1 last * |lt +rawAddress eq }' andif
- {
- 0 secondLast * STATICTYPED streq
- { 4 secondLast * sys .typed .type 0 eq }' andif
- 0 secondLast * PUSH streq
- { 1 secondLast * sys .typed .type 0 eq }' andif
- or
- }' andif
- {
- 0 thirdLast * STATICTYPED streq
- { 4 thirdLast * sys .typed .type 0 eq }' andif
- 0 thirdLast * PUSH streq
- { 1 thirdLast * sys .typed .type 0 eq }' andif
- or
- }' andif
- }' {
- [ NATIVE [
- /rcx :popqReg
- 63 /rcx :btrqImm8Reg
- [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
- 8 /rcx /rcx :movqMemDisp8Reg
-
- /rdx :popqReg
- 63 /rdx :btrqImm8Reg
- [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
- 8 /rdx /rdx :movqMemDisp8Reg
-
- /rsi /rsi :xorqRegReg
- /rcx /rdx :cmpqRegReg
-
- [ /rsi :incqReg ] len :jnlRel8
- /rsi :incqReg
-
- 63 /rsi :btsqImm8Reg
- /rsi :pushqReg
- ] ] i logic =[]
- [ NOP ] i 1 sub logic =[]
- }
- ] conds
+ { ==negatedOpcodeName ==functionName
+ { 1 last * functionName | +rawAddress eq }' {
+ [ NATIVE [
+ /rcx :popqReg
+ 63 /rcx :btrqImm8Reg
+ [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
+ 8 /rcx /rcx :movqMemDisp8Reg
+
+ /rdx :popqReg
+ 63 /rdx :btrqImm8Reg
+ [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
+ 8 /rdx /rdx :movqMemDisp8Reg
+
+ /rsi /rsi :xorqRegReg
+ /rcx /rdx :cmpqRegReg
+
+ [ /rsi :incqReg ] len negatedOpcodeName :
+ /rsi :incqReg
+
+ 63 /rsi :btsqImm8Reg
+ /rsi :pushqReg
+ ] ] i logic =[]
+ [ NOP ] i 1 sub logic =[]
+ }
+ } /logicalOperator deffst
+
+ /eq /jnzRel8 logicalOperator
+ /neq /jzRel8 logicalOperator
+ /le /jnleRel8 logicalOperator
+ /lt /jnlRel8 logicalOperator
+ /ge /jngeRel8 logicalOperator
+ /gt /jngRel8 logicalOperator
+ ] conds
+ } rep
} each
} /rewriteArithmetics deffst