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authorDrahflow <drahflow@gmx.de>2013-10-17 23:13:48 +0200
committerDrahflow <drahflow@gmx.de>2013-10-17 23:13:48 +0200
commit0554dbdfc5a20ef43281ec13e4442bedd2e3ae38 (patch)
treea68cc9a5ee0c94920a0345bb49d06e106e910387
parenteb9ed693fad8122a99f9cad8e9a496041be11f4b (diff)
Correctly handle more than 6 arguments
-rw-r--r--elymas/lib/sys/so.ey167
1 files changed, 97 insertions, 70 deletions
diff --git a/elymas/lib/sys/so.ey b/elymas/lib/sys/so.ey
index 1ce05c0..c1284a1 100644
--- a/elymas/lib/sys/so.ey
+++ b/elymas/lib/sys/so.ey
@@ -7,9 +7,6 @@
sys .asm .|peek =*:peek
sys .asm .|poke =*:poke
- { -1010 gt -021 ? } /max deffd
- { -1010 lt -021 ? } /min deffd
-
# hex decoding
{ # ==strNumber
0 -01 { 48 sub [ 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 10 11 12 13 14 15 ] * -01 16 mul -01 add } each
@@ -159,81 +156,104 @@
# 2 -> address of function
# the resulting function will take as many arguments as specified and return a single integer
{ ==rets ==args ==func
- [ /rdi /rsi /rdx /rcx /r8 /r9 ] =*:availableIntegerRegisters
+ [ /rdi /rsi /rdx /rcx /r8 /r9 ] _ =*:availableIntegerRegisters
+ len ==:INTREGISTERS
0 ==nextIntegerRegister
-
+
[
- args { ==t [
- { t 0 "i" * eq
- t 0 "p" * eq or }' {
- nextIntegerRegister availableIntegerRegisters ==reg
- nextIntegerRegister 1 add =nextIntegerRegister
-
- [
- reg :popqReg
- 63 reg :btrqImm8Reg
- [ 8 reg reg :movqMemDisp8Reg ] len :jcRel8
- 8 reg reg :movqMemDisp8Reg
- ]
- }
- { t 0 "b" * eq }' {
- nextIntegerRegister availableIntegerRegisters ==reg
+ 0 args len range { _ ==arg args * ==t
+ { # returns the register where the value is available
+ /rax ==reg
+ nextIntegerRegister INTREGISTERS lt {
+ nextIntegerRegister availableIntegerRegisters =reg
+ } rep
+ args len 1 sub arg sub 8 mul /rsp reg :movqMemDisp8Reg
+ reg
+ } /useIntegerStorage deffst
+
+ { # increments storage index, possibly do final stores
+ nextIntegerRegister INTREGISTERS ge {
+ /rax args len 1 sub arg sub 8 mul /rbp :movqRegMemDisp8
+ } rep
nextIntegerRegister 1 add =nextIntegerRegister
+ } /nextIntegerStorage deffst
- [
- reg :popqReg
- 24 reg :addqImm8Reg
- ]
- }
- { t 0 "s" * eq }' {
- nextIntegerRegister availableIntegerRegisters ==reg
- nextIntegerRegister 1 add =nextIntegerRegister
-
- {
- 0 24 1 /rax reg :andbImmMemIndexScaleDisp8
- 24 reg :addqImm8Reg
- } =*finalZeroSpaceAvailable
-
- {
- 0 nextIntegerRegister 1 sub range { availableIntegerRegisters :pushqReg } each
-
- reg :pushqReg
- 1 /rax /rdi :leaqMemDisp8Reg
- ::internalAllocateString /rax :movqImmReg
- /rax :callqReg
+ {
+ 0 nextIntegerRegister 6 min range { availableIntegerRegisters :pushqReg } each
+ } /pushIntegerStorage deffst
- 24 /rax /rdi :leaqMemDisp8Reg
+ {
+ 0 nextIntegerRegister 6 min range reverse { availableIntegerRegisters :popqReg } each
+ } /popIntegerStorage deffst
- /rax :popqReg
- 24 /rax /rsi :leaqMemDisp8Reg
- 16 /rax /rcx :movqMemDisp8Reg
- :reprcx :movsb
- 0 /rsi :andbImmMem
- 24 /rax reg :leaqMemDisp8Reg
-
- 0 nextIntegerRegister 1 sub range reverse { availableIntegerRegisters :popqReg } each
- } =*finalZeroSpaceNotAvailable
-
- [
- reg :popqReg
- 16 reg /rax :movqMemDisp8Reg
- 7 /al :testbImmReg
+ [
+ { t 0 "i" * eq
+ t 0 "p" * eq or }' {
[
- finalZeroSpaceNotAvailable
- 0 :jmpRel8
- ] len :jnzRel8
- finalZeroSpaceNotAvailable
+ useIntegerStorage ==reg
+ 63 reg :btrqImm8Reg
+ [ 8 reg reg :movqMemDisp8Reg ] len :jcRel8
+ 8 reg reg :movqMemDisp8Reg
+ nextIntegerStorage
+ ]
+ }
+ { t 0 "b" * eq }' {
[
+ useIntegerStorage ==reg
+ 24 reg :addqImm8Reg
+ nextIntegerStorage
+ ]
+ }
+ { t 0 "s" * eq }' {
+ [
+ useIntegerStorage ==reg
+
+ {
+ 0 24 1 /rax reg :andbImmMemIndexScaleDisp8
+ 24 reg :addqImm8Reg
+ } =*finalZeroSpaceAvailable
+
+ {
+ pushIntegerStorage
+
+ reg :pushqReg
+ 1 /rax /rdi :leaqMemDisp8Reg
+ ::internalAllocateString /rax :movqImmReg
+ /rax :callqReg
+
+ 24 /rax /rdi :leaqMemDisp8Reg
+
+ /rax :popqReg
+ 24 /rax /rsi :leaqMemDisp8Reg
+ 16 /rax /rcx :movqMemDisp8Reg
+ :reprcx :movsb
+ 0 /rsi :andbImmMem
+ 24 /rax reg :leaqMemDisp8Reg
+
+ popIntegerStorage
+ } =*finalZeroSpaceNotAvailable
+
+ 16 reg /rax :movqMemDisp8Reg
+ 7 /al :testbImmReg
+ [
+ finalZeroSpaceNotAvailable
+ 0 :jmpRel8
+ ] len :jnzRel8
+ finalZeroSpaceNotAvailable
+ [
+ finalZeroSpaceAvailable
+ ] len :jmpRel8
finalZeroSpaceAvailable
- ] len :jmpRel8
- finalZeroSpaceAvailable
- ]
- }
- { 1 }' {
- t dump
- "unknown argument semantics argument" die
- }
- ] conds } each
+
+ nextIntegerStorage
+ ]
+ }
+ { 1 }' {
+ t dump
+ "unknown argument semantics argument" die
+ }
+ ] conds
+ } each
] ==argumentLoaders
{
@@ -335,7 +355,14 @@
r15backup rawContentAddress /rax :movqImmReg
/r15 /rax :movqRegMem
- argumentLoaders reverse { _ len dearray } each
+ args len INTREGISTERS ge {
+ /rsp /rbp :movqRegReg
+ INTREGISTERS 8 mul /rbp :addqImm8Reg
+ %F0 /rbp :andqImm8Reg
+ } rep
+
+ argumentLoaders { _ len dearray } each
+ args len INTREGISTERS min 8 mul /rsp :addqImm8Reg
/rsp /rbp :movqRegReg
%F0 /rsp :andqImm8Reg