path: root/samyle/decoder.ey

<
  utils "$$" via
  txt .consume .|hu "%" defq
  txt .produce "$>" via
  sys .linux "+" via

  0 ==:GPR

  { <
    _ ==startA ==a
    0 ==prefix66
    0 ==prefix67
    0 ==operandWidth
    64 ==addressWidth
    0 ==rex
    0 ==rexW
    0 ==rexB
    0 ==rexR
    0 ==rexX
    1 neg ==rm
    1 neg ==reg
    1 neg ==mode
    1 neg ==dir
    1 neg ==imm
    1 neg ==target
    1 neg ==scale
    1 neg ==base
    1 neg ==idx
    0 ==hasDisp
    1 neg ==disp
    1 neg ==immWidth
    0 ==hasImmediate
    "???" ==instruction
    { [ instruction ] } /parts deffst

    { _ sys .typed .type 7 eq { |partsToTxt each } |cat ? * } /partsToTxt deffst
    { "" parts partsToTxt } /txt deffst

    { _ sys .typed .type 7 eq { |partsToCount each 1 add } { -- } ? * } /partsToCount deffst
    { 0 parts partsToCount } /partCount deffst

    { ==selected 0 ==any 0 ==p
      { 0 ==sel _ sys .typed .type 7 eq {
        selected p eq _ =sel { "" -01 1 =any } rep p 1 add =p |partsToTxtSelect each sel { "" } rep } |cat ? *
      } /partsToTxtSelect deffst
      "" parts partsToTxtSelect
      any not { "" "" } rep
    } /txtPartSelect deffst

    1 ==prefixDecoding
    { prefixDecoding 0 =prefixDecoding } {
      a $$memory %66 eq { 1 =prefix66 a 1 add =a 1 =prefixDecoding } rep
      a $$memory %67 eq { 1 =prefix67 a 1 add =a 1 =prefixDecoding } rep
    } loop

    prefix67 { 32 =addressWidth } rep

    a $$memory %F0 band %40 eq {
      a $$memory =rex
      rex 1 band 1 0 ? =rexB
      rex 2 band 1 0 ? =rexX
      rex 4 band 1 0 ? =rexR
      rex 8 band 1 0 ? =rexW
      a 1 add =a
    } rep

    { ==a
      a $$memory ==sib
      sib %07 band        rexB 8 mul add =base
      sib %38 band  8 div rexX 8 mul add =idx
      sib %C0 band 64 div [ 1 2 4 8 ] * =scale

      idx 4 eq { 1 neg =idx } rep
      idx 5 eq { 1 neg =base } rep

      a 1 add =a
      a
    } /decodeSib deffst

    { ==a
      a $$memory ==modrm
      modrm %07 band        rexB 8 mul add _ =rm =base
      modrm %38 band  8 div rexR 8 mul add =reg
      modrm %C0 band 64 div                =mode
      a 1 add =a

      mode 3 eq { 1 neg =base } rep

      mode 3 neq rm 7 band 4 eq and {
        a decodeSib =a
      } rep
      mode 2 eq {
        a a 4 add range $$memory 256 math .unbase =disp 1 =hasDisp a 4 add =a
        disp 2147483648 ge { disp 4294967296 neg bor =disp } rep
      } rep
      mode 1 eq {
        a $$memory =disp 1 =hasDisp a 1 add =a
        disp 128 ge { disp 256 neg bor =disp } rep
      } rep
      mode 0 eq rm 5 eq and {
        a a 4 add range $$memory 256 math .unbase =disp 1 =hasDisp a 4 add =a
        disp 2147483648 ge { disp 4294967296 neg bor =disp } rep
        16 =base
      } rep

      a
    } /decodeRegisterModrm deffst

    { ==width ==reg
      [
        { 8 width eq } { reg [ /al /cl /dl /bl ] rex [ /spl /bpl /sil /dil ] [ /ah /ch /dh /bh ] ? cat
                             [ /r8l /r9l /r10l /r11l /r12l /r13l /r14l /r15l "??? [rip 8 bit]" ] cat * }
        { 16 width eq } { reg [ /ax /cx /dx /bx /sp /bp /si /di /r8w /r9w /r10w /r11w /r12w /r13w /r14w /r15w "??? [rip 16 bit]" ] * }
        { 32 width eq } { reg [ /eax /ecx /edx /ebx /esp /ebp /esi /edi /r8d /r9d /r10d /r11d /r12d /r13d /r14d /r15d "??? [rip 32 bit]" ] * }
        { 64 width eq } { reg [ /rax /rcx /rdx /rbx /rsp /rbp /rsi /rdi /r8 /r9 /r10 /r11 /r12 /r13 /r14 /r15 /rip ] * }
        { 1 } { "??? [gprName]" }
      ] conds
    } /gprName deffd

    { a startA sub } /length deffst
    { [ [ instruction ] " " dir { gprRmParts ", " gprRegParts } { gprRegParts ", " gprRmParts } ? * ] } /gpi2opParts deffst
    { [ "%" reg operandWidth gprName cat ] } /gprRegParts deffst
    { [
      { mode 3 eq } { [ "%" rm operandWidth gprName cat ] }
      { mode 3 lt } { [
        hasDisp { disp dispParts } rep
        base 0 ge idx 0 ge or { "("
          base 0 ge { [ "%" base addressWidth gprName ] } rep
          idx 0 ge {
            ", " [ "%" idx addressWidth gprName ]
            scale 1 neq { ", " [ scale $>u ] } rep
          } rep
        ")" } rep
      ] }
      { 1 } { "??? [rm]" }
    ] conds } /gprRmParts deffst
    { # ==n
      _   [ -01 16 mod "0123456789abcdef" * ] str .fromArray
      -01 16 div
    } /extractHexDigit deffd
    { ==n [ [
      { operandWidth  8 eq } { [ n  2 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { operandWidth 16 eq } { [ n  4 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { operandWidth 32 eq } { [ n  8 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { operandWidth 64 eq } { [ n 16 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { 1 } { "??? [immParts]" }
    ] conds ] } /immParts deffst
    { ==n [ [
      { addressWidth  8 eq } { [ n  2 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { addressWidth 16 eq } { [ n  4 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { addressWidth 32 eq } { [ n  8 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { addressWidth 64 eq } { [ n 16 |extractHexDigit rep -- "$0x" ] reverse |cat fold }
      { 1 } { "??? [dispParts]" }
    ] conds ] } /dispParts deffst
    { [
      target $>hu _ locations .names .has {
        _ " = " cat -01 locations .names * cat
      } rep
    ] } /targetParts deffst

    {
      32 =operandWidth
      prefix66 { 16 =operandWidth } { } ? *
      rex { 64 =operandWidth } { } ? *

      |gpi2opParts =parts
      a decodeRegisterModrm =a
    } /gpi2Op deffst
    {
      8 =operandWidth

      |gpi2opParts =parts
      a decodeRegisterModrm =a
    } /gpi82Op deffst
    {
      32 =operandWidth
      prefix66 { 16 =operandWidth } { } ? *
      rex { 64 =operandWidth } { } ? *

      { [ [ instruction ] " " gprRmParts ] } =parts
      a decodeRegisterModrm =a
    } /gpi1Op deffst
    {
      32 =operandWidth
      prefix66 { 16 =operandWidth } { } ? *
      rex { 64 =operandWidth } { } ? *

      a decodeRegisterModrm =a 1 neg =reg # register field used to select opcodes
      1 =hasImmediate
      a $$memory =imm a 1 add =a
      { [ [ instruction ] " " imm immParts ", " gprRmParts ] } =parts
      imm 128 ge { imm 256 neg bor =imm } rep
    } /gpiImm8Op deffst
    {
      8 =operandWidth

      a decodeRegisterModrm =a 1 neg =reg # register field used to select opcodes
      1 =hasImmediate
      a $$memory =imm a 1 add =a
      { [ [ instruction ] " " imm immParts ", " gprRmParts ] } =parts
      imm 128 ge { imm 256 neg bor =imm } rep
    } /gpi8ImmOp deffst
    {
      32 =operandWidth
      prefix66 { 16 =operandWidth } { } ? *
      rex { 64 =operandWidth } { } ? *

      a decodeRegisterModrm =a 1 neg =reg # register field used to select opcodes
      1 =hasImmediate
      operandWidth 64 eq 32 operandWidth ? =immWidth
      a a immWidth 8 div add range $$memory 256 math .unbase =imm a immWidth 8 div add =a
      { [ [ instruction ] " " imm immParts ", " gprRmParts ] } =parts
      operandWidth 64 eq imm 2147483648 ge and { imm 4294967296 neg bor =imm } rep
    } /gpiImmOp deffst
    {
      { [ [ instruction ] " " gprRegParts ] } =parts
      64 =operandWidth
    } /popOp deffst
    {
      32 =operandWidth
      prefix66 { 16 =operandWidth } { } ? *
      rex { 64 =operandWidth } { } ? *

      1 =hasImmediate
      operandWidth =immWidth
      a a immWidth 8 div add range $$memory 256 math .unbase =imm a immWidth 8 div add =a
      { [ [ instruction ] " " imm immParts ", " gprRegParts ] } =parts
    } /movIOp deffst
    {
      32 _ =operandWidth =immWidth
      prefix66 { 16 _ =operandWidth =immWidth } { } ? *
      rex { 64 =operandWidth } { } ? *
      0 =reg

      1 =hasImmediate
      a a immWidth 8 div add range $$memory 256 math .unbase =imm a immWidth 8 div add =a
      immWidth 32 eq imm 2147483648 ge and { imm 4294967296 neg bor =imm } rep
      immWidth 16 eq imm      32768 ge and { imm      65536 neg bor =imm } rep
      { [ [ instruction ] " " imm immParts ", " gprRegParts ] } =parts
    } /axImmOp deffst
    {
      8 _ =operandWidth =immWidth
      0 =reg

      1 =hasImmediate
      a a immWidth 8 div add range $$memory 256 math .unbase =imm a immWidth 8 div add =a
      imm 128 ge { imm 256 neg bor =imm } rep
      { [ [ instruction ] " " imm immParts ", " gprRegParts ] } =parts
    } /ax8ImmOp deffst
    {
      64 =operandWidth
      32 =immWidth
      prefix66 { 16 =immWidth } { } ? *

      a a immWidth 8 div add range $$memory 256 math .unbase =imm a immWidth 8 div add =a
      immWidth 32 eq imm 2147483648 ge and { imm 4294967296 neg bor =imm } rep
      immWidth 16 eq imm      32768 ge and { imm      65536 neg bor =imm } rep
      { [ [ instruction ] " " targetParts ] } =parts
      a imm add =target
    } /callOp deffst
    {
      { [ instruction ] } =parts
    } /trivialOp deffst
    {
      64 =operandWidth
      8 =immWidth
      a $$memory =imm a 1 add =a
      imm 128 ge { imm 256 neg bor =imm } rep
      { [ [ instruction ] " " targetParts ] } =parts
      a imm add =target
    } /jcc8Op deffst

    a $$memory ==opcode
    a 1 add =a
    a $$memory _ ==secondaryOpcode
                 %38 band 8 div ==modrmOpcode
    a 1 add $$memory %38 band 8 div ==modrmOpcode2

    [
      { opcode %00 eq } { "add" =instruction 0 =dir gpi82Op }
      { opcode %01 eq } { "add" =instruction 0 =dir gpi2Op }
      { opcode %02 eq } { "add" =instruction 1 =dir gpi82Op }
      { opcode %03 eq } { "add" =instruction 1 =dir gpi2Op }
      { opcode %04 eq } { "add" =instruction ax8ImmOp }
      { opcode %05 eq } { "add" =instruction axImmOp }
      { opcode %06 eq } { "push %es (invalid in 64bit)" trivialOp }
      { opcode %07 eq } { "pop %es (invalid in 64bit)" trivialOp }
      { opcode %08 eq } { "or" =instruction 0 =dir gpi82Op }
      { opcode %09 eq } { "or" =instruction 0 =dir gpi2Op }
      { opcode %0A eq } { "or" =instruction 1 =dir gpi82Op }
      { opcode %0B eq } { "or" =instruction 1 =dir gpi2Op }
      { opcode %0C eq } { "or" =instruction ax8ImmOp }
      { opcode %0D eq } { "or" =instruction axImmOp }
      { opcode %0E eq } { "push %cs (invalid in 64bit)" trivialOp }
      { opcode %0F eq secondaryOpcode %1F eq and modrmOpcode2 0 eq and } { a 1 add =a "nop" =instruction gpi1Op }
      # TODO insert secondary opcode map

      { opcode %10 eq } { "adc" =instruction 0 =dir gpi82Op }
      { opcode %11 eq } { "adc" =instruction 0 =dir gpi2Op }
      { opcode %12 eq } { "adc" =instruction 1 =dir gpi82Op }
      { opcode %13 eq } { "adc" =instruction 1 =dir gpi2Op }
      { opcode %14 eq } { "adc" =instruction ax8ImmOp }
      { opcode %15 eq } { "adc" =instruction axImmOp }
      { opcode %16 eq } { "push %ss (invalid in 64bit)" trivialOp }
      { opcode %17 eq } { "pop %ss (invalid in 64bit)" trivialOp }
      { opcode %18 eq } { "sbb" =instruction 0 =dir gpi82Op }
      { opcode %19 eq } { "sbb" =instruction 0 =dir gpi2Op }
      { opcode %1A eq } { "sbb" =instruction 1 =dir gpi82Op }
      { opcode %1B eq } { "sbb" =instruction 1 =dir gpi2Op }
      { opcode %1C eq } { "sbb" =instruction ax8ImmOp }
      { opcode %1D eq } { "sbb" =instruction axImmOp }
      { opcode %1E eq } { "push %ds (invalid in 64bit)" trivialOp }
      { opcode %1F eq } { "pop %ds (invalid in 64bit)" trivialOp }

      { opcode %20 eq } { "and" =instruction 0 =dir gpi82Op }
      { opcode %21 eq } { "and" =instruction 0 =dir gpi2Op }
      { opcode %22 eq } { "and" =instruction 1 =dir gpi82Op }
      { opcode %23 eq } { "and" =instruction 1 =dir gpi2Op }
      { opcode %24 eq } { "and" =instruction ax8ImmOp }
      { opcode %25 eq } { "and" =instruction axImmOp }
      { opcode %26 eq } { "%es segment prefix (nop in 64bit)" trivialOp }
      { opcode %27 eq } { "daa (invalid in 64bit)" trivialOp }
      { opcode %28 eq } { "sub" =instruction 0 =dir gpi82Op }
      { opcode %29 eq } { "sub" =instruction 0 =dir gpi2Op }
      { opcode %2A eq } { "sub" =instruction 1 =dir gpi82Op }
      { opcode %2B eq } { "sub" =instruction 1 =dir gpi2Op }
      { opcode %2C eq } { "sub" =instruction ax8ImmOp }
      { opcode %2D eq } { "sub" =instruction axImmOp }
      { opcode %2E eq } { "%cs segment prefix (nop in 64bit)" trivialOp }
      { opcode %2F eq } { "das (invalid in 64bit)" trivialOp }

      { opcode %30 eq } { "xor" =instruction 0 =dir gpi82Op }
      { opcode %31 eq } { "xor" =instruction 0 =dir gpi2Op }
      { opcode %32 eq } { "xor" =instruction 1 =dir gpi82Op }
      { opcode %33 eq } { "xor" =instruction 1 =dir gpi2Op }
      { opcode %34 eq } { "xor" =instruction ax8ImmOp }
      { opcode %35 eq } { "xor" =instruction axImmOp }
      { opcode %36 eq } { "%ss segment prefix (nop in 64bit)" trivialOp }
      { opcode %37 eq } { "aaa (invalid in 64bit)" trivialOp }
      { opcode %38 eq } { "cmp" =instruction 0 =dir gpi82Op }
      { opcode %39 eq } { "cmp" =instruction 0 =dir gpi2Op }
      { opcode %3A eq } { "cmp" =instruction 1 =dir gpi82Op }
      { opcode %3B eq } { "cmp" =instruction 1 =dir gpi2Op }
      { opcode %3C eq } { "cmp" =instruction ax8ImmOp }
      { opcode %3D eq } { "cmp" =instruction axImmOp }
      { opcode %3E eq } { "%ds segment prefix (nop in 64bit)" trivialOp }
      { opcode %3F eq } { "aas (invalid in 64bit)" trivialOp }

      { opcode %50 eq } { "push" =instruction 0 rexR 8 mul add =reg popOp }
      { opcode %51 eq } { "push" =instruction 1 rexR 8 mul add =reg popOp }
      { opcode %52 eq } { "push" =instruction 2 rexR 8 mul add =reg popOp }
      { opcode %53 eq } { "push" =instruction 3 rexR 8 mul add =reg popOp }
      { opcode %54 eq } { "push" =instruction 4 rexR 8 mul add =reg popOp }
      { opcode %55 eq } { "push" =instruction 5 rexR 8 mul add =reg popOp }
      { opcode %56 eq } { "push" =instruction 6 rexR 8 mul add =reg popOp }
      { opcode %57 eq } { "push" =instruction 7 rexR 8 mul add =reg popOp }
      { opcode %58 eq } { "pop" =instruction 0 rexR 8 mul add =reg popOp }
      { opcode %59 eq } { "pop" =instruction 1 rexR 8 mul add =reg popOp }
      { opcode %5A eq } { "pop" =instruction 2 rexR 8 mul add =reg popOp }
      { opcode %5B eq } { "pop" =instruction 3 rexR 8 mul add =reg popOp }
      { opcode %5C eq } { "pop" =instruction 4 rexR 8 mul add =reg popOp }
      { opcode %5D eq } { "pop" =instruction 5 rexR 8 mul add =reg popOp }
      { opcode %5E eq } { "pop" =instruction 6 rexR 8 mul add =reg popOp }
      { opcode %5F eq } { "pop" =instruction 7 rexR 8 mul add =reg popOp }

      { opcode %60 eq } { "pusha (invalid in 64bit)" =instruction trivialOp }
      { opcode %61 eq } { "popa (invalid in 64bit)" =instruction trivialOp }
      { opcode %62 eq } { "bound (invalid in 64bit)" =instruction trivialOp }
      # TODO

      { opcode %70 eq } { "jo" =instruction jcc8Op }
      { opcode %71 eq } { "jno" =instruction jcc8Op }
      { opcode %72 eq } { "jc" =instruction jcc8Op }
      { opcode %73 eq } { "jnc" =instruction jcc8Op }
      { opcode %74 eq } { "jz" =instruction jcc8Op }
      { opcode %75 eq } { "jnz" =instruction jcc8Op }
      { opcode %76 eq } { "jbe" =instruction jcc8Op }
      { opcode %77 eq } { "ja" =instruction jcc8Op }
      { opcode %78 eq } { "js" =instruction jcc8Op }
      { opcode %79 eq } { "jns" =instruction jcc8Op }
      { opcode %7A eq } { "jp" =instruction jcc8Op }
      { opcode %7B eq } { "jnp" =instruction jcc8Op }
      { opcode %7C eq } { "jl" =instruction jcc8Op }
      { opcode %7D eq } { "jge" =instruction jcc8Op }
      { opcode %7E eq } { "jle" =instruction jcc8Op }
      { opcode %7F eq } { "jg" =instruction jcc8Op }

      { opcode %80 eq modrmOpcode 7 eq and } { "cmp" =instruction gpi8ImmOp }
      { opcode %83 eq modrmOpcode 0 eq and } { "add" =instruction gpiImm8Op }
      { opcode %83 eq modrmOpcode 4 eq and } { "and" =instruction gpiImm8Op }
      { opcode %83 eq modrmOpcode 5 eq and } { "sub" =instruction gpiImm8Op }
      { opcode %83 eq modrmOpcode 7 eq and } { "cmp" =instruction gpiImm8Op }
      { opcode %85 eq } { "test" =instruction 0 =dir gpi2Op }
      { opcode %89 eq } { "mov" =instruction 0 =dir gpi2Op }
      { opcode %8B eq } { "mov" =instruction 1 =dir gpi2Op }
      { opcode %8D eq } { "lea" =instruction 1 =dir gpi2Op }
      { opcode %B8 eq } { "mov" =instruction 0 rexR 8 mul add =reg movIOp }
      { opcode %B9 eq } { "mov" =instruction 1 rexR 8 mul add =reg movIOp }
      { opcode %BA eq } { "mov" =instruction 2 rexR 8 mul add =reg movIOp }
      { opcode %BB eq } { "mov" =instruction 3 rexR 8 mul add =reg movIOp }
      { opcode %BC eq } { "mov" =instruction 4 rexR 8 mul add =reg movIOp }
      { opcode %BD eq } { "mov" =instruction 5 rexR 8 mul add =reg movIOp }
      { opcode %BE eq } { "mov" =instruction 6 rexR 8 mul add =reg movIOp }
      { opcode %BF eq } { "mov" =instruction 7 rexR 8 mul add =reg movIOp }
      { opcode %C1 eq modrmOpcode 5 eq and } { "shr" =instruction gpiImm8Op }
      { opcode %C1 eq modrmOpcode 7 eq and } { "sar" =instruction gpiImm8Op }
      { opcode %C3 eq } { "ret" =instruction trivialOp }
      { opcode %C6 eq modrmOpcode 0 eq and } { "mov" =instruction gpiImm8Op }
      { opcode %C7 eq modrmOpcode 0 eq and } { "mov" =instruction gpiImmOp }
      { opcode %C9 eq } { "leave" =instruction trivialOp }
      { opcode %D1 eq modrmOpcode 5 eq and } { "shr" =instruction gpi1Op }
      { opcode %D1 eq modrmOpcode 7 eq and } { "sar" =instruction gpi1Op }
      { opcode %E8 eq } { "call" =instruction callOp }
      { opcode %E9 eq } { "jmp" =instruction callOp }
      { opcode %F3 eq } { "repz" =instruction trivialOp }
      { opcode %F4 eq } { "hlt" =instruction trivialOp }
      { opcode %FF eq modrmOpcode 2 eq and } { "call" =instruction gpi1Op operandWidth 32 eq { 64 =operandWidth } rep }
      { opcode %FF eq modrmOpcode 4 eq and } { "jmp" =instruction gpi1Op operandWidth 32 eq { 64 =operandWidth } rep }
    ] conds
  > } /fromAddress deffd
> /decoder defvd

# vim: syn=elymas