From cd680c6d4bb37213e1dbe0df5c87c6f8ea1b04eb Mon Sep 17 00:00:00 2001
From: Drahflow <drahflow@gmx.de>
Date: Sun, 29 Sep 2013 13:19:43 +0200
Subject: 13% faster with (some) inline arithmetics

---
 compiler/elymasGlobalSysOpt.ey |  16 +++++
 elymas/lib/sys/opt.ey          | 158 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 174 insertions(+)

diff --git a/compiler/elymasGlobalSysOpt.ey b/compiler/elymasGlobalSysOpt.ey
index b3128bf..49d9282 100644
--- a/compiler/elymasGlobalSysOpt.ey
+++ b/compiler/elymasGlobalSysOpt.ey
@@ -104,6 +104,22 @@
       :retn
     ]] /eyreplace defv
 
+    # returns internalAllocateInteger into userspace
+    # 0 <- ::internalAllocateInteger as integer
+    [[
+      /rbx :popqReg
+
+      ::internalAllocateInteger /rax :movqImmReg
+      /rax :callqReg
+      /rax :pushqReg
+
+      ::internalAllocateInteger /rdx :movqImmReg
+      /rdx 8 /rax :movqRegMemDisp8
+
+      /rbx :pushqReg
+      :retn
+    ]] /eyinternalAllocateInteger defv
+
     # returns internalAllocateScope into userspace
     # 0 <- ::internalAllocateScope as integer
     [[
diff --git a/elymas/lib/sys/opt.ey b/elymas/lib/sys/opt.ey
index a1c835f..8ac7980 100644
--- a/elymas/lib/sys/opt.ey
+++ b/elymas/lib/sys/opt.ey
@@ -244,6 +244,163 @@
       } each
     } /rewriteConstantDot deffst
 
+    { _ ==logic
+      3 logic len range { ==i
+        i logic * ==entry
+        0 entry * ==action
+        i 1 sub logic * ==last
+        i 2 sub logic * ==secondLast
+        i 3 sub logic * ==thirdLast
+
+        [
+          { action CALL streq
+            { 1 entry * "*" | +rawCodeAddress eq }' andif
+            { 0 last * PUSH streq }' andif
+              { 1 last * |add +rawAddress eq }' andif
+            {
+              0 secondLast * STATICTYPED streq
+                { 4 secondLast * sys .typed .type 0 eq }' andif
+              0 secondLast * PUSH streq
+                { 1 secondLast * sys .typed .type 0 eq }' andif
+              or
+            }' andif
+            {
+              0 thirdLast * STATICTYPED streq
+                { 4 thirdLast * sys .typed .type 0 eq }' andif
+              0 thirdLast * PUSH streq
+                { 1 thirdLast * sys .typed .type 0 eq }' andif
+              or
+            }' andif
+          }' {
+            [ NATIVE [
+              /rcx :popqReg
+              63 /rcx :btrqImm8Reg
+              [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
+              8 /rcx /rcx :movqMemDisp8Reg
+
+              /rdx :popqReg
+              63 /rdx :btrqImm8Reg
+              [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
+              8 /rdx /rdx :movqMemDisp8Reg
+
+              /rcx /rdx :addqRegReg
+
+              /rdx /rax :movqRegReg
+              32 /rax :shrqImm8Reg
+              
+              [
+                63 /rdx :btsqImm8Reg
+                /rdx :pushqReg
+                0 :jmpRel8
+              ] len :jnzRel8
+
+              63 /rdx :btsqImm8Reg
+              /rdx :pushqReg
+
+              [
+                /rdx :pushqReg
+                ::internalAllocateInteger /rax :movqImmReg
+                /rax :callqReg
+                8 /rax :popqMemDisp8
+                /rax :pushqReg
+              ] len :jmpRel8
+
+              /rdx :pushqReg
+              ::internalAllocateInteger /rax :movqImmReg
+              /rax :callqReg
+              8 /rax :popqMemDisp8
+              /rax :pushqReg
+            ] ] i logic =[]
+            [ NOP ] i 1 sub logic =[]
+          }
+
+          { action CALL streq
+            { 1 entry * "*" | +rawCodeAddress eq }' andif
+            { 0 last * PUSH streq }' andif
+              { 1 last * |le +rawAddress eq }' andif
+            {
+              0 secondLast * STATICTYPED streq
+                { 4 secondLast * sys .typed .type 0 eq }' andif
+              0 secondLast * PUSH streq
+                { 1 secondLast * sys .typed .type 0 eq }' andif
+              or
+            }' andif
+            {
+              0 thirdLast * STATICTYPED streq
+                { 4 thirdLast * sys .typed .type 0 eq }' andif
+              0 thirdLast * PUSH streq
+                { 1 thirdLast * sys .typed .type 0 eq }' andif
+              or
+            }' andif
+          }' {
+            [ NATIVE [
+              /rcx :popqReg
+              63 /rcx :btrqImm8Reg
+              [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
+              8 /rcx /rcx :movqMemDisp8Reg
+
+              /rdx :popqReg
+              63 /rdx :btrqImm8Reg
+              [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
+              8 /rdx /rdx :movqMemDisp8Reg
+
+              /rsi /rsi :xorqRegReg
+              /rcx /rdx :cmpqRegReg
+
+              [ /rsi :incqReg ] len :jnleRel8
+              /rsi :incqReg
+
+              63 /rsi :btsqImm8Reg
+              /rsi :pushqReg
+            ] ] i logic =[]
+            [ NOP ] i 1 sub logic =[]
+          }
+
+          { action CALL streq
+            { 1 entry * "*" | +rawCodeAddress eq }' andif
+            { 0 last * PUSH streq }' andif
+              { 1 last * |lt +rawAddress eq }' andif
+            {
+              0 secondLast * STATICTYPED streq
+                { 4 secondLast * sys .typed .type 0 eq }' andif
+              0 secondLast * PUSH streq
+                { 1 secondLast * sys .typed .type 0 eq }' andif
+              or
+            }' andif
+            {
+              0 thirdLast * STATICTYPED streq
+                { 4 thirdLast * sys .typed .type 0 eq }' andif
+              0 thirdLast * PUSH streq
+                { 1 thirdLast * sys .typed .type 0 eq }' andif
+              or
+            }' andif
+          }' {
+            [ NATIVE [
+              /rcx :popqReg
+              63 /rcx :btrqImm8Reg
+              [ 8 /rcx /rcx :movqMemDisp8Reg ] len :jcRel8
+              8 /rcx /rcx :movqMemDisp8Reg
+
+              /rdx :popqReg
+              63 /rdx :btrqImm8Reg
+              [ 8 /rdx /rdx :movqMemDisp8Reg ] len :jcRel8
+              8 /rdx /rdx :movqMemDisp8Reg
+
+              /rsi /rsi :xorqRegReg
+              /rcx /rdx :cmpqRegReg
+
+              [ /rsi :incqReg ] len :jnlRel8
+              /rsi :incqReg
+
+              63 /rsi :btsqImm8Reg
+              /rsi :pushqReg
+            ] ] i logic =[]
+            [ NOP ] i 1 sub logic =[]
+          }
+        ] conds
+      } each
+    } /rewriteArithmetics deffst
+
     { _ ==logic
       1 logic len range { ==i i logic * ==entry 0 entry * ==action i 1 sub logic * ==last
         [
@@ -531,6 +688,7 @@
       rewriteConstantEquals
     } rep
     rewriteConstantDot
+    rewriteArithmetics
     rewriteConstantStar
     rewriteStackOps
     { =*entry 0 entry ==action
-- 
cgit v1.2.3